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general description features ics9248-64 block diagram 9248-64 rev b 12/03/99 pin configuration 48-pin ssop amd-k is a trademark of advanced micro devices. ? generates the following system clocks: - 3 differential pair open drain cpu clocks (1.5v external pull-up; up to 133mhz). - 8 pci including 1 free running (3.3v) @33.3mhz. - 2 agp(3.3v) up to 66.6mhz. - 2 ref(3.3v)@14.318mhz - 1 48mhz(3.3v) - 24 / 48mhz(3.3v) skew characteristics: - cpu -cpu <250ps - cput - cpuc <200ps (differential pair) - pci ? pci: <500ps - cpu ? sdram_out: < 250ps - cpu ? agp <500ps efficient power management through pd#, pci_stop# and cpu_stop#. spread spectrum option for emi reduction (-0.5% down spread). uses external 14.318 mhz crystal the ics9248-64 is a main clock synthesizer chip for amd- k7 based systems. this provides all clocks required for such a system when used with a zero delay buffer chip such as the ics9179-06. spread spectrum may be enabled by driving the spread# pin active. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248-64 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. *fs0/ref0 *fs1/ref1 gndref x1 x2 gndpci pciclk_f pciclk0 vddpci pciclk1 pciclk2 gndpci pciclk3 pciclk4 vddpci pciclk5 pciclk6 vddagp agp0 agp1 gndagp vdd48 48mhz sel24_48#/24-48mhz vddref gndsd sdram_out vddsd reserved cpuclkc2 cpuclkt2 gndcpu cuclkc1 cpuclkt1 gnd cpuclkc0 cpuclkt0 reserved vdd gnd pci_stop# cpu_stop# pd# spread# test# s data sclk gnd48 ics9248-64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 { i c 2 amd-k7 tm system clock chip * internal 120k pullup resistor on indicated inputs ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ics9248-64 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 2 , 1 ) 1 : 0 ( s fn id d v o t p u - l l u p s a h , s n i p t c e l e s y c n e u q e r f ) 1 : 0 ( f e rt u ot u p t u o k c o l c z h m 8 1 3 . 4 1 3f e r d n gr w ps t u p t u o f e r r o f d n u o r g 41 xn i d a o l f p 3 3 l a n r e t n i s a h , t u p n i l a t s y r c z h m 8 1 3 . 4 1 n i _ l a t x 2 x m o r f r o t s i s e r k c a b d e e f d n a p a c 52 xt u of p 3 3 p a c d a o l l a n r e t n i s a h , t u p t u o l a t s y r c t u o _ l a t x 2 1 , 6i c p d n gr w ps t u p t u o i c p r o f d n u o r g 7f _ k l c i c pt u o # p o t s _ i c p e h t y b d e t c e f f a t o n . t u p t u o i c p g n i n n u r e e r f . t u p n i , 3 1 , 1 1 , 0 1 , 8 7 1 , 6 1 , 4 1 ) 6 : 0 ( k l c i c pt u ov 3 . 3 e l b i t a p m o c l t t . s t u p t u o k c o l c i c p 5 1 , 9i c p d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o k l c i c p r o f r e w o p 8 1p g a d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o p g a r o f r e w o p 0 2 , 9 1) 1 : 0 ( p g at u o. d e p p o t s e b t o n y a m e s e h t . i c p x 2 s a d e n i f e d s t u p t u o p g a 1 2p g a d n gr w ps t u p t u o k c o l c p g a r o f d n u o r g 2 28 4 d d vr w pv 3 . 3 y l l a n i m o n s t u p t u o c d f , b s u r o f r e w o p 3 2z h m 8 4t u ot u p t u o z h m 8 4 4 2 # 8 4 - 4 2 l e sn i 4 2 n i p r o f t u p t u o z h m 8 4 r o 4 2 s t c e l e s z h m 4 2 = h g i h z h m 8 4 = w o l z h m 8 4 - 4 2t u o# 8 4 - 4 2 l e s h g u o r h t e l b a t c e l e s t u o k c o l c d e x i f 5 28 4 d n gr w ps t u p t u o z h m 8 4 r o f d n u o r g 6 2k l c sn ii r o f t u p n i k c o l c 2 c 7 2a t a d sn ii r o f t u p n i a t a d 2 c 8 2# t s e tn i w o l n e h w e d o m t s e t r o e t a t s i r t ) e l b a t y c n e u q e r f o t r e f e r e s a e l p ( 9 2# d a e r p sn i d a e r p s n w o d . w o l n e h w e r u t a e f m u r t c e p s d a e r p s s e l b a n e z h k 0 5 = y c n e u q e r f n o i t a l u d o m % 5 . 0 0 3# d pn i e r a s t u p t u o l l a & l l p l a n r e t n i . w o l e v i t c a , p i h c n w o d s r e w o p . d e l b a s i d 1 3# p o t s _ u p cn i s a e r e h w w o l n e v i r d s i ) 2 : 0 ( t k l c u p c . s k l c u p c s t l a h d e t r e s s a s i n i p s i h t n e h w h g i h n e v i r d s i ) 2 : 0 ( c k l c u p c . ) w o l e v i t c a ( 2 3# p o t s _ i c pn i f _ k l c i c p . w o l n e v i r d n e h w l e v e l " 0 " c i g o l t a s u b i c p s t l a h n i p s i h t y b d e t c e f f a t o n s i 3 3d n gr w pe r o c r o f d n u o r g d e t a l o s i 4 3d d vr w pv 3 . 3 y l l a n i m o n , e r o c r o f r e w o p d e t a l o s i 4 4 , 5 3d e v r e s e rc / nl i a r r e w o p u p c e r u t r u f , 2 4 , 9 3 , 6 3) 2 : 0 ( t k l c u p ct u o n e p o e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . p u - l l u p v 5 . 1 l a n r e t x e n a d e e n s t u p t u o n i a r d 3 4 , 0 4 , 7 3) 2 : 0 ( c k l c u p ct u o e s e h t . t u p t u o u p c r i a p l a t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c " . p u _ l l u p v 5 . 1 l a n r e t x e n a d e e n s t u p t u o n i a r d n e p o 1 4 , 8 3u p c d n gr w p. s t u p t u o k l c u p c r o f d n u o r g 5 4d s d d vr w pv 3 . 3 y l l a n i m r o n . n i p t u o _ m a r d s r o f r e w o p 6 4t u o _ m a r d st u or e f f u b y a l e d o r e z m a r d s r o f k c o l c e c n e r e f e r 7 4d s d n gr w ps n i p t u o _ m a r d s r o f d n u o r g 8 4f e r d d vr w pv 3 . 3 y l l a n i m o n , 2 x , 1 x , ) 1 : 0 ( f e r r o f r e w o p
ics9248-64 notes: 1. tclk is a test clock driven on the x1 (crystal in pin) input during test mode. frequency select # t s e t1 s f0 s f , u p c m a r d s i c pp g az h m 8 4f e rs t n e m m o c 000 z - i hz - i hz - i hz - i hz - i he t a t s - i r t 001 0 . 0 50 . 5 20 . 0 58 48 1 3 . 4 1 010 6 . 6 63 . 3 36 . 6 68 48 1 3 . 4 1 011 2 / k l c t6 / k l c t3 / k l c t4 / k l c tk l c t) 1 ( e d o m t s e t 100 0 . 0 90 . 0 30 . 0 68 48 1 3 . 4 1 101 3 . 3 3 13 . 3 36 . 6 68 48 1 3 . 4 1 110 0 . 0 2 10 . 0 30 . 0 68 48 1 3 . 4 1 111 0 . 0 0 13 . 3 36 . 6 68 48 1 3 . 4 1
ics9248-64 i 2 c command bitmaps byte 0: reserved for buffer t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) r e f f u b r o f d e v r e s e r ( 6 t i b-1 ) r e f f u b r o f d e v r e s e r ( 5 t i b-1 ) r e f f u b r o f d e v r e s e r ( 4 t i b-1 ) r e f f u b r o f d e v r e s e r ( 3 t i b-1 ) r e f f u b r o f d e v r e s e r ( 2 t i b-1 ) r e f f u b r o f d e v r e s e r ( 1 t i b-1 ) r e f f u b r o f d e v r e s e r ( 0 t i b-1 ) r e f f u b r o f d e v r e s e r ( byte 1: reserved for buffer t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) r e f f u b r o f d e v r e s e r ( 6 t i b-1 ) r e f f u b r o f d e v r e s e r ( 5 t i b-1 ) r e f f u b r o f d e v r e s e r ( 4 t i b-1 ) r e f f u b r o f d e v r e s e r ( 3 t i b-1 ) r e f f u b r o f d e v r e s e r ( 2 t i b-1 ) r e f f u b r o f d e v r e s e r ( 1 t i b-1 ) r e f f u b r o f d e v r e s e r ( 0 t i b-1 ) r e f f u b r o f d e v r e s e r ( byte 2: reserved for buffer t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) r e f f u b r o f d e v r e s e r ( 6 t i b-1 ) r e f f u b r o f d e v r e s e r ( 5 t i b-1 ) r e f f u b r o f d e v r e s e r ( 4 t i b-1 ) r e f f u b r o f d e v r e s e r ( 3 t i b-1 ) r e f f u b r o f d e v r e s e r ( 2 t i b-1 ) r e f f u b r o f d e v r e s e r ( 1 t i b-1 ) r e f f u b r o f d e v r e s e r ( 0 t i b-1 ) r e f f u b r o f d e v r e s e r ( byte 3: reserved for buffer t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) r e f f u b r o f d e v r e s e r ( 6 t i b-1 ) r e f f u b r o f d e v r e s e r ( 5 t i b-1 ) r e f f u b r o f d e v r e s e r ( 4 t i b-1 ) r e f f u b r o f d e v r e s e r ( 3 t i b-1 ) r e f f u b r o f d e v r e s e r ( 2 t i b-1 ) r e f f u b r o f d e v r e s e r ( 1 t i b-1 ) r e f f u b r o f d e v r e s e r ( 0 t i b-1 ) r e f f u b r o f d e v r e s e r (
ics9248-64 byte 4: clock control register notes: a value of '1'b is enable, '0'b is disable byte 6: sdram clock & generator mode control register notes: a value of '1'b is enable, '0'b is disable t i bn o i t p i r c s e dd w p 7d a e r p s n w o d % 5 . 0 - e l b a n e m u r t c e p s d a e r p s1 4 : 6 t i b 4 5 6 u p ci c pe g a t n e c r e p d a e r p s 1 1 1 0 1 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 2 1 3 3 1 0 9 2 / k l c t 6 6 0 5 z - i h 3 . 3 3 0 3 3 . 3 3 0 3 6 / k l c t 3 3 5 2 z - i h d a e r p s n w o d % 1 d a e r p s n w o d % 1 d a e r p s n w o d % 1 d a e r p s n w o d % 1 d a e r p s n w o d % 1 d a e r p s n w o d % 1 d a e r p s n w o d % 1 d a e r p s n w o d % 1 1 3 : 2) d e v r e s e r (1 1i 2 e l b a n e c1 0e l b a n e t u o _ m a r d s1 t i b# n i pd w pn o i t p i r c s e d 711 e l b a n e 0 f e r 64 21 e l b a n e z h m 8 4 / z h m 4 2 53 21 e l b a n e z h m 8 4 40 21 e l b a n e 1 p g a 39 11 e l b a n e 0 p g a 23 4 , 2 41 f o h t o b ( e l b a n e 2 k l c u p c d n a " e u r t , r i a p l a i t n e r e f f i d " y r a t n e m i l p m o c " 10 4 , 9 31 f o h t o b ( e l b a n e 1 k l c u p c d n a " e u r t , r i a p l a i t n e r e f f i d " y r a t n e m i l p m o c " 07 3 , 6 31 f o h t o b ( e l b a n e 0 k l c u p c d n a " e u r t , r i a p l a i t n e r e f f i d " y r a t n e m i l p m o c " byte 5: pci clock control register notes: a value of '1'b is enable, '0'b is disable t i b# n i pd w pn o i t p i r c s e d 721 e l b a n e 1 f e r 67 11 e l b a n e 6 k l c i c p 56 11 e l b a n e 5 k l c i c p 44 11 e l b a n e 4 k l c i c p 33 11 e l b a n e 3 k l c i c p 21 11 e l b a n e 2 k l c i c p 10 11 e l b a n e 1 k l c i c p 081 e l b a n e 0 k l c i c p
ics9248-64 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70 o c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input frequency f i v dd = 3.3 v; 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t cpu-sdram vt = 50% 190 250 ps t cpu-agp vt = 50% 60 500 ps 1 guaranteed by design, not 100% tested in production. skew1 180 ma input capacitance 1 operating supply current
ics9248-64 electrical characteristics - cpuclk (open drain) t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance z o v o = v x 50 ? output high voltage v oh2b termination to v pull-up(external) 11.2v output low voltage v ol2b termination to v pull-up(external) 0.175 0.4 v output low current i ol2b v ol = 0.3 v 18 21 ma rise time 1 t r2b v ol = 0.3 v, v oh = 1.2 v 0.85 0.9 ns differential voltage- ac 1 v dif note 2 0.4 v pullup(external) + 0.6 v differential voltage- dc 1 v dif note 2 0.2 v pullup(external) + 0.6 v differential crossover voltage 1 v x note 3 550 750 1100 mv duty cycle 1 d t2b v t = 50% 45 51 55 % skew 1 , cpu to cpu t sk2b v t = 50% 100 250 ps skew 1 , cput to cpuc t sk2b v t = 50% 135 200 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = v x 110 250 ps notes: 1 - guaranteed by design, not 100% tested in production. 3 - vpullup (external) = 1.5v, min = vpullup (external) /2-150mv; max=(vpullup (external) /2)+150mv 2 - v dif specifies the minimum input differential voltages (v tr -v cp ) required for switching, where v tr is the "true" input level and v cp is the "complement" input level. electrical characteristics - 24_48m, ref(0:1) t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 2.8 v output low voltage v ol5 i ol = 9 ma 0.32 0.4 v output high current i oh5 v oh = 2.0 v -27 -22 ma output low current i ol5 v ol = 0.8 v 16 22 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 2.3 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 2.4 4 ns duty cycle 1 d t5 v t = 50% 45 51 55 % v t = 1.5 volts, ref 400 1000 ps v t = 1.5 volts, usb, 24_48m 260 500 ps 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc1
ics9248-64 electrical characteristics - pciclk_f t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.6 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.165 0.4 v output high current i oh1 v oh = 2.0 v -54 -12 ma output low current i ol1 v ol = 0.8 v 12 44 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.75 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.65 2 ns duty cycle 1 d t1 v t = 50% 45 51 55 % jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 volts 120 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk(0:6) t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.6 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.17 0.4 v output high current i oh1 v oh = 2.0 v -54 -16 ma output low current i ol1 v ol = 0.8 v 19 44 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.8 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.65 2 ns duty cycle 1 d t1 v t = 50% 45 51 55 % skew 1 (window) t sk 1 v t = 50% 470 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 volts 120 500 ps 1 guaranteed by design, not 100% tested in production.
ics9248-64 electrical characteristics - agp(0:1) t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -18 ma 2 3 v output low voltage v ol4b i ol = 18 ma 0.31 0.4 v output high current i oh4b v oh = 2.0 v -63 -19 ma output low current i ol4b v ol = 0.8 v 19 30 ma rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 1.3 2 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 1.4 2 ns duty cycle 1 d t4b v t = 50% 45 50 55 % jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 volts 290 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram_out t a = 0 - 70 o c; v dd = 3.3 v +/-5%, c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -11 ma 2 3 v output low voltage v ol3 i ol = 11 ma 0.31 0.4 v output high current i oh3 v oh = 2.0 v -60 -12 ma output low current i ol3 v ol = 0.8 v 12 30 ma rise time 1 t r3 1 v ol = 0.4 v, v oh = 2.4 v 1.7 2.2 ns fall time 1 t f3 1 v oh = 2.4 v, v ol = 0.4 v 1.9 2.2 ns duty cycle 1 d t3 1 v t = 50% 45 55 55 % jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 volts 130 250 ps 1 guarenteed by design, not 100% tested in production.

ics9248-64 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write:

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" how to read:

#

" controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit h ow to read: controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit h ow to write:
ics9248-64 fig. 1 shared pin operation - input/output pins $ %& "
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2 5 ", 6& " , "*" " " ", " 7 " " via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k 8 2 " " 9 :" " " 9 :" " " " " - $ " ; " " , "
ics9248-64 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248-64 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclkt cpuclkc pciclk vco crystal pd#
ics9248-64 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-64 . all other clocks will continue to run while the cpuclks clocks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9248-64 . 3. all other clocks continue to run undisturbed including sdramr. 4. pd# and pci_stop# are shown in a high (true) state. pciclk cpuclkt cpuclkc pci_stop# (high) cpu_stop# pd# (high) internal cpuclk
ics9248-64 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-64 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ics9248-64 internally. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state. cpuclk (internal) pciclk (internal) pciclk (free-running) cpu_stop# pwr_dwn# pciclk (external) pci_stop#
ics9248-64 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9248 y f-64 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp .093 dia. pin (optional) d/2 e/2 bottom view a 1 -e- b a side view -c- -d- seating plane a 2 see detail ?a? -e- c end view parting line l detail ?a? h pin 1 top view index area l o b m y ss n o i s n e m i d n o m m o cs n o i t a i r a vdn . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .2 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a7 8 0 .0 9 0 .4 9 0 . b8 0 0 .- 5 3 1 0 . c5 0 0 .- 5 8 0 0 . ds n o i t a i r a v e e s e1 9 2 .5 9 2 .9 9 2 . ec s b 5 2 0 . 0 h5 9 3 .-0 2 4 . h0 1 0 .3 1 0 .6 1 0 . l0 2 0 .-0 4 0 . ns n o i t a i r a v e e s 0- 8 48 pin 300 mil ssop package ?for current dimensional specifications, see jedec 95.?

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